/* $Author: dshi$ */
/* $email:  dshi7@wisc.edu$ */
module proc (/*AUTOARG*/
	        // Outputs
	        err,
	        // Inputs
	        clk, rst
	     );
   input clk;
   input rst;
   output err;

      // None of the above lines can be modified

      // OR all the err ouputs for every sub-module and assign it as this
      // err output

      // As desribed in the homeworks, use the err signal to trap corner
      // cases that you think are illegal in your statemachines


      /* your code here */

        wire    [15:0]  pc_in;
        wire            createdump;   
        wire    [15:0]  inst;
        wire    [15:0]  pc_plus_2_if_id;
        wire    [15:0]  pc_plus_2_id_ex;
        wire    [15:0]  pc_plus_2_ex_mem;
        wire    [15:0]  pc_plus_2_mem_wb;
        wire    [15:0]  rf1_id_ex;
        wire    [15:0]  rf2_id_ex;
        wire    [15:0]  rf1_ex_mem;
        wire    [10:0]  inst_id_ex;
        wire    [8:0]   inst_ex_mem;
        wire    [8:0]   inst_mem_wb;
        wire    [19:0]  id_ex;
        wire    [11:0]  ex_mem;
        wire    [3:0]   mem_wb;
        wire    [15:0]  alu_out;
        wire    [15:0]  immd16;
        wire    [15:0]  mem_out;
        wire    [15:0]  lbi_out;
        

        FETCH   fetch 
        (
                .pc_in ( pc_in ),
                .createdump ( createdump ),
                .clk ( clk ),
                .rst ( rst ),
                .inst ( inst ),
                .addr_out ( pc_plus_2_if_id ),
                .err ( err )
        );
        DECODE  decode
        (       
                .addr_in ( pc_plus_2_if_id ),
                .inst ( inst ),
                .reg_wr ( reg_wr ),
                .reg_wr_data ( reg_wr_data ),
                .reg_wr_addr ( reg_wr_addr ),
                .clk ( clk ),
                .rst ( rst ),
                .createdump ( createdump ),
                .id_ex ( id_ex ),
                .addr_out ( pc_plus_2_id_ex ),
                .rd_data1 ( rf1_id_ex ),
                .rd_data2 ( rf2_id_ex ),
                .inst_pl ( inst_id_ex ),
                .err ( err )
        );
        EXEC    exec
        (
                .id_ex ( id_ex );
                .addr_in ( pc_plus_2_id_ex ),
                .rf1 ( rf1_id_ex ),
                .rf2 ( rf2_id_ex ),
                .inst ( inst_id_ex ),
                .clk ( clk ),
                .rst ( rst ),
                .ex_mem ( ex_mem ),
                .addr_out ( pc_plus_2_ex_mem ),
                .alu_out_pl ( alu_out ),
                .rf1_pl ( rf1_ex_mem ),
                .ext_pl (immd16 ),
                .inst_pl ( inst_ex_mem ),
                .err ( err )
        );
        MEMORY  memory
        (
                .em_mem ( ex_mem ),
                .addr_in ( pc_plus_2_ex_mem ),
                .alu_out_pl ( alu_out ),
                .rf1_pl ( rf1_ex_mem ),
                .ext_pl ( immd16 ),
                .inst ( inst_ex_mem ),
                .createdump ( createdump ),
                .clk ( clk ),
                .rst ( rst ),
                .mem_wb ( mem_wb ),
                .addr_out_pl ( pc_plus_2_mem_wb ),
                .addr_out ( pc_in ),
                .mem_pl ( mem_out ),
                .lbi ( lbi_out ),
                .inst_pl ( inst_mem_wb ),
                .err ( err )
        );
        WRBACK  writeback
        (
                .mem_wb ( mem_wb ),
                .addr_in ( pc_plus_2_mem_wb ),
                .mem_pl ( mem_out ),
                .lbi ( lbi_out ),
                .inst_pl ( inst_mem_wb ),
                .clk ( clk ),
                .rst ( rst ),
                .reg_wr ( reg_wr ),
                .reg_wr_data ( reg_wr_data ),
                .reg_wr_addr ( reg_wr_addr ),
                .err ( err )
        );
endmodule // proc
// DUMMY LINE FOR REV CONTROL :0:
